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1/14 july 2001 n high speed: f max = 59mhz (typ.) at v cc = 6v n low power dissipation: i cc = 4 m a(max.) at t a =25c n high noise immunity: v nih = v nil = 28 % v cc (min.) n symmetrical output impedance: |i oh | = i ol = 6ma (min.) for qa to qh |i oh | = i ol = 4ma (min.) for qh n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 595 description the m74hc595 is an high speed cmos 8-bit shift registers/output latches (3-state) fabricated with silicon gate c 2 mos technology. this device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit d-type storage register. the storage register has 8 3-state outputs. separate clocks are provided for both the shift register and the storage register. the shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. both the shift register and storage register use positive-edge triggered clocks. if both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc595 8 bit shift register with output latches (3 state) pin connection and iec logic symbols order codes package tube t & r dip m74hc595b1r sop m74hc595m1r m74hc595rm13tr tssop M74HC595TTR tssop dip sop
m74hc595 2/14 input and output equivalent circuit pin description truth table x: dont care logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1, 2, 3, 4, 5, 6, 7, 15 qa to qh data outputs 9 qh serial data outputs 10 sclr shift register clear input 11 sck shift register clock input 13 g output enable input 14 si serial data input 12 rck storage register clock input 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs si sck sclr rck g xxxxh qa thru qh out puts disable xxxxl qa thru qh out puts enable x x l x x shift register is cleared lhxx first stage of s.r. becomes "l" other stages store the data of previous stage, respectively hhxx first stage of s.r. becomes "h" other stages store the data of previous stage, respectively x h x x state of s.r. is not changed xxx x s.r. data is stored into storage register x x x x storage register state is not changed
m74hc595 3/14 logic diagram this logic diagram has not be used to estimate propagation delays timing chart
m74hc595 4/14 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc595 5/14 dc specifications symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage (for qh outputs) 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-6.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-7.8 ma 5.68 5.8 5.63 5.60 v oh high level output voltage (for qa to qh outputs) 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-6.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-7.8 ma 5.68 5.8 5.63 5.60 v ol low level output voltage (for qh outputs) 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =6.0 ma 0.17 0.26 0.33 0.40 6.0 i o =7.8 ma 0.18 0.26 0.33 0.40 v ol low level output voltage (for qa to qh outputs) 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =6.0 ma 0.17 0.26 0.33 0.40 6.0 i o =7.8 ma 0.18 0.26 0.33 0.40 i i input leakage current 6.0 v i = v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 6.0 v i = v ih or v il v o = v cc or gnd 0.5 5 10 m a i cc quiescent supply current 6.0 v i = v cc or gnd 44080 m a
m74hc595 6/14 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time (qn) 2.0 50 25 60 75 90 ns 4.5 7121518 6.0 6101315 t tlh t thl output transition time (qh) 2.0 50 30 75 95 115 ns 4.5 8151923 6.0 7131620 t plh t phl propagation delay time (sck - qh) 2.0 50 45 125 155 190 ns 4.5 15 25 31 38 6.0 13 21 26 32 t plh t phl propagation delay time (sclr - qh) 2.0 50 60 175 220 265 ns 4.5 18 35 44 53 6.0 15 30 37 45 t plh t phl propagation delay time (rck - qn) 2.0 50 60 150 190 225 ns 4.5 20 30 38 45 6.0 17 26 32 38 2.0 150 75 190 240 285 ns 4.5 25 38 48 57 6.0 22 32 41 48 t pzl t pzh high impedance output enable time 2.0 50 r l = 1 k w 45 135 170 205 ns 4.5 15 27 34 41 6.0 13 23 29 35 2.0 150 r l = 1 k w 60 175 220 265 ns 4.5 20 35 44 53 6.0 17 30 37 45 t plz t phz high impedance output disable time 2.0 50 r l = 1 k w 30 150 190 225 ns 4.5 15 30 38 45 6.0 14 26 32 38 f max maximum clock frequency 2.0 50 6.0 17 4.8 4 mhz 4.5 30 50 24 20 6.0 35 59 28 24 2.0 150 5.2 14 4.2 3.4 mhz 4.5 26 40 21 17 6.0 31 45 25 20 t w(h) minimum pulse width (sck, rck) 2.0 50 17 75 95 110 ns 4.5 6151922 6.0 6131619 t w(l) minimum pulse width (sclr ) 2.0 50 20 75 95 110 ns 4.5 6151922 6.0 6131619 t s minimum set-up time (si - cck) 2.0 50 25 50 65 75 ns 4.5 5101315 6.0 4 9 11 13 t s minimum set-up time (sck - rck) 2.0 50 35 75 95 110 ns 4.5 8151922 6.0 6131619
m74hc595 7/14 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 = 1k w or equivalent r t = z out of pulse generator (typically 50 w ) t s minimum set-up time (scrl - rck) 2.0 50 40 100 125 145 ns 4.5 10 20 25 29 6.0 7172125 t h minimum hold time 2.0 50 000 ns 4.5 0 0 0 6.0 0 0 0 t rem minimum clear removal time 2.0 50 15 50 65 75 ns 4.5 3101315 6.0 3 9 11 13 symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c pd power dissipation capacitance (note 1) 184 pf test switch t plh , t phl open t pzl , t plz v cc t pzh , t phz gnd symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max.
m74hc595 8/14 waveform 1 : sck to qh propagation delay times, sck minimum pulse width (f=1mhz; 50% duty cycle) waveform 2 : rck to qn propagation delay times (f=1mhz; 50% duty cycle) waveform 3 : si to sck setup and hold times (f=1mhz; 50% duty cycle)
m74hc595 9/14 waveform 4 : sck to rck setup and hold times (f=1mhz; 50% duty cycle) waveform 5 : sclr minimum pulse width, minimum removal time (f=1mhz; 50% duty cycle)
m74hc595 10/14 waveform 6 : output enable and disable times (f=1mhz; 50% duty cycle) waveform 7 : input waveform (f=1mhz; 50% duty cycle)
m74hc595 11/14 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
m74hc595 12/14 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
m74hc595 13/14 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
m74hc595 14/14 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com

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